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M58LW032C
32 Mbit (2Mb x16, Uniform Block, Burst) 3V Supply Flash Memory
FEATURES SUMMARY s WIDE x16 DATA BUS for HIGH BANDWIDTH
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Figure 1. Packages
SUPPLY VOLTAGE - VDD = 2.7 to 3.6V core supply voltage for Program, Erase and Read operations
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- VDDQ = 1.8 to VDD for I/O Buffers SYNCHRONOUS/ASYNCHRONOUS READ - Synchronous Burst read - Asynchronous Random Read - Asynchronous Address Latch Controlled Read - Page Read
TSOP56 (N) 14 x 20 mm
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ACCESS TIME - Synchronous Burst Read up to 56MHz - Asynchronous Page Mode Read 90/25ns, 110/25ns - Random Read 90ns, 110ns
TBGA
TBGA64 (ZA) 10 x 13 mm
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PROGRAMMING TIME - 16 Word Write Buffer - 12s Word effective programming time
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32 UNIFORM 64 KWord MEMORY BLOCKS ENHANCED SECURITY - Block Protection/ Unprotection - Smart Protection: irreversible block locking system - VPEN signal for Program Erase Enable - 128 bit Protection Register with 64 bit Unique Code in OTP area
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PROGRAM and ERASE SUSPEND COMMON FLASH INTERFACE 100,000 PROGRAM/ERASE CYCLES per BLOCK ELECTRONIC SIGNATURE - Manufacturer Code: 0020h - Device Code M58LW032C : 8822h
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April 2003
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M58LW032C
TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TSOP56 Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. TBGA64 Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Inputs (A1-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Inputs/Outputs (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset/Power-Down (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Valid Data Ready (R). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Status/(Ready/Busy) (STS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Program/Erase Enable (VPEN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Latch Controlled Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Random Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Asynchronous Page Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Synchronous Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Synchronous Burst Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Single Synchronous Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 X-Latency Bits (CR13-CR11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Internal Clock Divider Bit (CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Y-Latency Bit (CR9). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Valid Data Ready Bit (CR8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Burst Type Bit (CR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Valid Clock Edge Bit (CR6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Burst Length Bit (CR2-CR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Burst Configuration X-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 7. Burst Configuration X-2-2-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Memory Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Query Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Write to Buffer and Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Set Configuration Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block Protect Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Blocks Unprotect Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configure STS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6. Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7. Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 8. Read Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 8. Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 9. Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 25 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Erase Suspend Status Bit ( SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 VPEN Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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Reserved (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 10. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 9. AC Measurement Input Output Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 10. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 11. Asynchronous Bus Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 15. Asynchronous Bus Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 33 Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics . . . . . . . . . . . . . . . . . . . 33 Figure 13. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 17. Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled . . . . . . . . . . . . . . . . . . . 35 Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled . . . . . . 35 Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . 37 Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled . . . . . 37 Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 18. Synchronous Burst Read AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output . . . . . . . . . . . . . . . 40 Table 20. Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 20. Reset, Power-Down and Power-up AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 21. Reset, Power-Down and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 41 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline . . . . . . . Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Outline . . . . . . . . . . . . . . . . Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data . . . . . . . . . 42 42 43 43
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 24. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 25. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 APPENDIX B. COMMON FLASH INTERFACE - CFI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Table 27. CFI - Query Address and Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 28. CFI - Device Voltage and Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 29. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 30. Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 31. Extended Query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 47 47 48 49
APPENDIX C. FLOW CHARTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 23. Write to Buffer and Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . Figure 24. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . Figure 25. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . Figure 27. Block Protect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28. Blocks Unprotect Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 29. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . Figure 30. Command Interface and Program Erase Controller Flowchart (a) . . . . . . . . . . . . . . . . Figure 31. Command Interface and Program Erase Controller Flowchart (b) . . . . . . . . . . . . . . . . Figure 32. Command Interface and Program Erase Controller Flowchart (c). . . . . . . . . . . . . . . . 50 51 52 53 54 55 56 57 58 59
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 32. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
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SUMMARY DESCRIPTION M58LW032C is a 32 Mbit (2Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7V to 3.6V) core supply. On power-up the memory defaults to Read mode with an asynchronous bus where it can be read in the same way as a non-burst Flash memory. The memory is divided into 32 blocks of 1Mbit that can be erased independently so it is possible to preserve valid data while old data is erased. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a Program or Erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In asynchronous mode an Address Latch input can be used to latch addresses in Latch Controlled mode. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 56MHz. The Write Buffer allows the microprocessor to program from 1 to 16 Words in parallel, both speeding up the programming and freeing up the microprocessor to perform other work. A Word Program command is available to program a single Word. Erase can be suspended in order to perform either Read or Program in any other block and then resumed. Program can be suspended to Read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles. The M58LW032C has several security features to increase data protection.
Block Protection, where each block can be individually protected against program or erase operations. All blocks are protected during power-up. The protection of the blocks is nonvolatile; after power-up the protection status of each block is restored to the state when power was last removed. s Program Erase Enable input VPEN, program or erase operations are not possible when the Program Erase Enable input VPEN is low. s Smart Protection, which allows protected blocks to be permanently locked. This feature is not described in the datasheet for security reasons. Please contact STMicroelectronics for further details. s 128 bit Protection Register, divided into two 64 bit segments: the first contains a unique device number written by ST, the second is user programmable. The user programmable segment can be protected. The Reset/Power-Down pin is used to apply a Hardware Reset to the memory and to set the device in power-down mode. The device features an Auto Low Power mode. If the bus becomes inactive during Asynchronous Read operations, the device automatically enters Auto Low Power mode. In this mode the power consumption is reduced to the Auto Low Power supply current. The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: Ready/ Busy mode where a static signal indicates the status of the P/E.C, and Status mode where a pulsing signal indicates the end of a Program or Block Erase operation. In Status mode it can be used as a system interrupt signal, useful for saving CPU time. The memory is available in TSOP56 (14 x 20 mm) and TBGA64 (10 x 13mm, 1mm pitch) packages.
s
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Figure 2. Logic Diagram
VDD VDDQ
Table 1. Signal Names
A1-A21 DQ0-DQ15 E G Address inputs Data Inputs/Outputs Chip Enable Output Enable Clock Latch Enable Valid Data Ready Status/(Ready/Busy) Reset/Power-Down Program/Erase Enable Write Enable Supply Voltage Input/Output Supply Voltage Ground Input/Output Ground Not Connected Internally
21 A1-A21
K L
VPEN 16 W E G RP L K M58LW032C DQ0-DQ15 STS R
R STS RP
VPEN
W VDD VDDQ VSS VSSQ NC
VSS VSSQ
AI06208
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Figure 3. TSOP56 Connections
NC R A21 A20 A19 A18 A17 A16 VDD A15 A14 A13 A12 E VPEN RP A11 A10 A9 A8 VSS A7 A6 A5 A4 A3 A2 A1
1
56
NC W G STS DQ15 DQ7 DQ14 DQ6 VSS DQ13 DQ5 DQ12 DQ4 VDDQ VSSQ DQ11 DQ3 DQ10 DQ2 VDD DQ9 DQ1 DQ8 DQ0 NC K NC L
AI06209
14 43 M58LW032C 15 42
28
29
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Figure 4. TBGA64 Connections (Top view through package)
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPEN
A13
VDD
A18
NC
B
A2
VSS
A9
E
A14
NC
A19
R
C
A3
A7
A10
A12
A15
NC
A20
A21
D
A4
A5
A11
RP
NC
NC
A16
A17
E
DQ8
DQ1
DQ9
DQ3
DQ4
NC
DQ15
STS
F
K
DQ0
DQ10
DQ11
DQ12
NC
NC
G
G
NC
NC
DQ2
VDDQ
DQ5
DQ6
DQ14
W
H
L
NC
VDD
VSS
DQ13
VSSQ
DQ7
NC
AI06210b
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Figure 5. Block Addresses
Word (x16) Bus Width 1FFFFFh 1F0000h 1EFFFFh 1E0000h Total of 32 1 Mbit Blocks
1 Mbit or 64 KWords 1 Mbit or 64 KWords
01FFFFh 010000h 00FFFFh 000000h
1 Mbit or 64 KWords 1 Mbit or 64 KWords
AI06254
Note: Also see Appendix A, Table 25 for a full listing of the Block Addresses.
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SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram and Table 11, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A1-A21). The Address Inputs are used to select the cells to access in the memory array during Bus Read operations either to read or to program data to. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Chip Enable and Latch Enable must be low when selecting the addresses. The address inputs are latched on the rising edge of Chip Enable, Write Enable or Latch Enable, whichever occurs first in a Write operation. The address latch is transparent when Latch Enable is low, VIL. The address is internally latched in an Erase or Program operation. Data Inputs/Outputs (DQ0-DQ15). The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation, or are used to input the data during a program operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. When used to input data or Write commands they are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. When Chip Enable and Output Enable are both low, V IL, the data bus outputs data from the memory array, the Electronic Signature, the Block Protection status, the CFI Information or the contents of the Status Register. The data bus is high impedance when the chip is deselected, Output Enable is high, VIH, or the Reset/Power-Down signal is low, V IL. When the Program/Erase Controller is active the Ready/Busy status is given on DQ7. Chip Enable (E). The Chip Enable, E, input activates the memory control logic, input buffers, decoders and sense amplifiers. Chip Enable, E, at VIH deselects the memory and reduces the power consumption to the Standby level, IDD1. Output Enable (G). The Output Enable, G, gates the outputs through the data output buffers during a read operation. When Output Enable, G, is at VIH the outputs are high impedance. Output Enable, G, can be used to inhibit the data output during a burst read operation. Write Enable (W). The Write Enable input, W, controls writing to the Command Interface, Input Address and Data latches. Both addresses and data can be latched on the rising edge of Write Enable (also see Latch Enable, L). Reset/PowerReset/Power-Down (RP). The Down pin can be used to apply a Hardware Reset to the memory.
A Hardware Reset is achieved by holding Reset/ Power-Down Low, VIL, for at least tPLPH. When Reset/Power-Down is Low, VIL, the Status Register information is cleared and the power consumption is reduced to power-down level. The device is deselected and outputs are high impedance. If Reset/Power-Down goes low, V IL,during a Block Erase, a Write to Buffer and Program or a Block Protect/Unprotect the operation is aborted and the data may be corrupted. In this case the Ready/ Busy pin stays low, V IL, for a maximum timing of tPLPH + tPHRH, until the completion of the Reset/ Power-Down pulse. After Reset/Power-Down goes High, V IH, the memory will be ready for Bus Read and Bus Write operations after tPHQV. Note that Ready/Busy does not fall during a reset, see Ready/Busy Output section. In an application, it is recommended to associate Reset/Power-Down pin, RP, with the reset signal of the microprocessor. Otherwise, if a reset operation occurs while the memory is performing an Erase or Program operation, the memory may output the Status Register information instead of being initialized to the default Asynchronous Random Read. Latch Enable (L). The Bus Interface is configured to latch the Address Inputs on the rising edge of Latch Enable, L. In synchronous bus operations the address is latched on the active edge of the Clock when Latch Enable is Low, V IL or on the rising of Latch Enable, whichever occurs first. Once latched, the addresses may change without affecting the address used by the memory. When Latch Enable is Low, VIL, the latch is transparent. Clock (K). The Clock, K, is used to synchronize the memory with the external bus during Synchronous Bus Read operations. The Clock can be configured to have an active rising or falling edge. Bus signals are latched on the active edge of the Clock during synchronous bus operations. In Synchronous Burst Read mode the address is latched on the first active clock edge when Latch Enable is low, VIL, or on the rising edge of Latch Enable, whichever occurs first. During asynchronous bus operations the Clock is not used. Valid Data Ready (R). The Valid Data Ready output, R, is an open drain output that can be used to identify if the memory is ready to output data or not. The Valid Data Ready output is only active during Synchronous Burst Read operations when the Burst Length is set to Continuous. The Valid Data Ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. Valid Data Ready Low, V OL, in-
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dicates that the data is not, or will not be valid. Valid Data Ready in a high-impedance state indicates that valid data is or will be available. Unless Synchronous Burst Read has been selected, Valid Data Ready is high-impedance. It may be tied to other components with the same Valid Data Ready signal to create a unique System Ready signal. The Valid Data Ready, R, output has an internal pull-up resistor of approximately 1 M powered from VDDQ, designers should use an external pullup resistor of the correct value to meet the external timing requirements for Valid Data Ready rising. Refer to Figure 19. Status/(Ready/Busy) (STS). The STS signal is an open drain output that can be used to identify the Program/Erase Controller status. It can be configured in two modes: s Ready/Busy - the pin is Low, VOL, during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation. s Status - the pin gives a pulsing signal to indicate the end of a Program or Block Erase operation. After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured for Status mode using the Configure STS command. When the Program/Erase Controller is idle, or suspended, STS can float High through a pull-up resistor. The use of an open-drain output allows the STS pins from several memories to be connected to a single pull-up resistor (a Low will indicate that one, or more, of the memories is busy). STS is not Low during a reset unless the reset was applied when the Program/Erase controller was active. Ready/Busy can rise before Reset/PowerDown rises. Program/Erase Enable (VPEN). The Program/ Erase Enable input, VPEN, is used to protect all blocks, preventing Program and Erase operations from affecting their data. Program/Erase Enable must be kept High during all Program/Erase Controller operations, otherwise the operations is not guaranteed to succeed and data may become corrupt. VDD Supply Voltage. VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. It is recommended to power-up and power-down VDD and VDDQ together to avoid any condition that would result in data corruption. VSS Ground. Ground, VSS, is the reference for the core power supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by V DDQ. VSSQ must be connected to V SS. Note: Each device in a system should have VDD and VDDQ decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 10, AC Measurement Load Circuit.
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BUS OPERATIONS There are six standard bus operations that control the device. These are Address Latch, Bus Read, Bus Write, Output Disable, Power-Down and Standby. See Table 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. Address Latch. Address latch operations input valid addresses. A valid bus operation involves setting the desired address on the Address Inputs, setting Chip Enable and Latch Enable Low, V IL and keeping Write Enable High, VIH; the address is latched on the rising edge of Address Latch. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register, the Common Flash Interface and the Block Protection Status. A valid bus operation involves setting the desired address on the Address Inputs, applying a Low signal, V IL, to Chip Enable, Output Enable and Latch Enable and keeping Write Enable High, V IH. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 11, 12, 13, 18 and 19 Read AC Waveforms, and Tables 15, 16, 17 and 20 Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write Commands to the memory or latch addresses and input data to be programmed. Table 2. Bus Operations
Operation Address Latch Bus Read Bus Write Output Disable Power-Down Standby E VIL VIL VIL VIL X VIH G X VIL VIH VIH X X W VIH VIH VIL VIH X X RP VIH VIH VIH VIH VIL VIH L VIL VIL VIL X X X A1-A21 Address Address Address X X X DQ0-DQ15 Data Output or Hi-Z (2) Data Output Data Input High Z High Z High Z
A valid Bus Write operation begins by setting the desired address on the Address Inputs and setting Latch Enable Low, V IL. The Address Inputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V IH, during the Bus Write operation. See Figures 14, 15, 16 and 17, Write AC Waveforms, and Tables 18 and 19, Write AC Characteristics, for details of the timing requirements. Output Disable. The The Data Inputs/Outputs are high impedance when the Output Enable is at VIH. Power-Down. The memory is in Power-Down mode when Reset/Power-Down, RP, is Low. The power consumption is reduced to the Power-Down level, IDD2, and the outputs are high impedance, independent of Chip Enable, Output Enable or Write Enable. Standby. Standby disables most of the internal circuitry, allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable is at VIH. The power consumption is reduced to the standby level IDD1 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to V IH during a program or erase operation, the device enters Standby mode when finished.
Note: 1. X = Don't Care VIL or VIH . 2. Depends on G
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READ MODES Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is `don't care' for the data output, the read operation is asynchronous; if the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (See Configuration Register section for details). On Power-up or after a Hardware Reset the memory defaults to Asynchronous Read mode. Asynchronous Read Modes In Asynchronous Read operations the clock signal is `don't care'. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface, Electronic Signature or Block Protection Status depending on the command issued. CR15 in the Configuration Register must be set to `1' for asynchronous operations. During Asynchronous Read operations, if the bus is inactive for a time equivalent to tAVQV, the device automatically enters Auto Low Power mode. In this mode the internal supply current is reduced to the Auto Low Power supply current, IDD5. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Automatic Low Power is only available in Asynchronous Read modes. Asynchronous Read operations can be performed in three different ways, Asynchronous Latch Controlled Read, Asynchronous Random Read and Asynchronous Page Read. Asynchronous Latch Controlled Read. In Asynchronous Latch Controlled Read operations read the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. A valid bus operation involves setting the desired address on the Address Inputs, setting Chip Enable and Latch Enable Low, V IL and keeping Write Enable High, VIH; the address is latched on the rising edge of Address Latch. Once latched, the Address Inputs can change. Set Output Enable Low, VIL, to read the data on the Data Inputs/Outputs; see Figure 12, Asynchronous Latch Controlled Read AC Waveforms and Table 16, Asynchronous Latch Controlled Read AC Characteristics for details on when the output becomes valid. See Figures 12, Asynchronous Latch Controlled Read AC Waveforms, and Table 16, Asynchronous Latch Controlled Read AC Characteristics, for details.
Asynchronous Random Read. As the Latch Enable input is transparent when set Low, V IL, Asynchronous Random Read operations can be performed by holding Latch Enable Low, VIL throughout the bus operation. See Figures 11, Asynchronous Random Read AC Waveforms, and Table 15, Asynchronous Random Read AC Characteristics, for details. Asynchronous Page Read. In Asynchronous Page Read mode a Page of data is internally read and stored in a Page Buffer. Each memory page is 4 Words and has the same A3-A22, only A1 and A2 may change. The first read operation within the Page has the normal access time (tAVQV), subsequent reads within the same Page have much shorter access times (tAVQV1). If the Page changes then the normal, longer timings apply again. See Figures 13, Asynchronous Page Read AC Waveforms, and Table 17, Asynchronous Page Read AC Characteristics, for details. Synchronous Read Modes In Synchronous Read mode the data output is synchronized with the clock. CR15 in the Configuration Register must be set to `0' for synchronous operations. Synchronous Burst Read. In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI, Read Electronic Signature and Block Protection Status, Single Synchronous Read or Asynchronous Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A valid Synchronous Burst Read operation begins when the address is set on the Address Inputs, Write Enable is High, VIH, and Chip Enable and Latch Enable are Low, V IL, during the active edge of the Clock. The address is latched on the first active clock edge when Latch Enable is low, or on the rising edge of Latch Enable, whichever occurs first. The data becomes available for output after the X-latency specified in the Burst Control Register has expired. The output buffers are activated by setting Output Enable Low, V IL. See Figures 6 and 7 for examples of Synchronous Burst Read operations. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4 Words, 8 Words or Continuous (Burst Length
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bits CR2-CR0). In Synchronous Continuous Burst Read mode one Burst Read operation can access the entire memory sequentially. If the starting address is not associated with a page (4 Word) boundary the Valid Data Ready, R, output goes Low, V IL, to indicate that the data will not be ready in time and additional wait-states are required. The Valid Data Ready output timing (bit CR8) can be changed in the Configuration Register. The order of the data output can be modified through the Burst Type bit in the Configuration Register. The burst sequence can be sequential or interleaved. See Table 20, Synchronous Read AC Characteristics and Figure 18 and 19, Synchronous Burst Read AC Waveform for details. Single Synchronous Read. Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Single Synchronous Reads are used to read the Status Register, CFI, Electronic Signature and Block Protection Status.
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CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will perform. The Configuration Register bits are described in Table 3. They specify the selection of the burst length, burst type, burst X and Y latencies and the Read operation. See figures 6 and 7 for examples of Synchronous Burst Read configurations. The Configuration Register is set through the Command Interface and will retain its information until it is re-configured, the device is reset, or the device goes into Reset/Power-Down mode. The Configuration Register is read using the Read Electronic Signature Command at address 05h. Read Select Bit (CR15). The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to '1', Bus Read operations are asynchronous; when the Read Select but is set to '0', Bus Read operations are synchronous. On reset or power-up the Read Select bit is set to '1' for asynchronous access. X-Latency Bits (CR13-CR11). The X-Latency bits are used during Synchronous Bus Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 3, Configuration Register. Internal Clock Divider Bit (CR10). The Internal Clock Divider Bit is used to divide the internal clock by two. When CR10 is set to `1' the internal clock is divided by two, which effectively means that the X and Y-Latency values are multiplied by two, that is the number of clock cycles between the address being latched and the first data becoming available will be twice the value set in CR13-CR11, and the number of clock cycles between consecutive reads will be twice the value set in CR9. For example 8-1-1-1 will become 16-2-2-2. When CR10 is set to `0' the internal clock runs normally and the X and Y-Latency values are those set in CR13-CR11 and CR9. Y-Latency Bit (CR9). The Y-Latency bit is used during Synchronous Bus Read operations to set
the number of clock cycles between consecutive reads. The Y-Latency value depends on both the X-Latency value and the setting in CR9. When the Y-Latency is 1 the data changes each clock cycle; when the Y-Latency is 2 the data changes every second clock cycle. See Table 3, Configuration Register for valid combinations of the Y-Latency, the X-Latency and the Clock frequency. Valid Data Ready Bit (CR8). The Valid Data Ready bit controls the timing of the Valid Data Ready output pin, R. When the Valid Data Ready bit is '0' the Valid Data Ready output pin is driven Low for the active clock edge when invalid data is output on the bus. When the Valid Data Ready bit is '1' the Valid Data Ready output pin is driven Low one clock cycle prior to invalid data being output on the bus. Burst Type Bit (CR7). The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is '0' the memory outputs from interleaved addresses; when the Burst Type bit is '1' the memory outputs from sequential addresses. See Tables 4, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (CR6). The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is '0' the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is '1' the rising edge of the Clock is active. Burst Length Bit (CR2-CR0). The Burst Length bits set the maximum number of Words that can be output during a Synchronous Burst Read operation. Table 3, Configuration Register gives the valid combinations of the Burst Length bits that the memory accepts; Tables 4, Burst Type Definition, give the sequence of addresses output from a given starting address for each length. CR5 CR4 and CR3 are reserved for future use.
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Table 3. Configuration Register
Address Bit 16 15 Mnemonic Bit Name Reset Value 1 1 CR14 001 010 14 to 12 011 CR13-CR11 X-Latency(2) XXX 100 101 110 Internal Clock Divider 0 X 1 10 CR9 Y-Latency(3) Valid Data Ready Burst Type Valid Clock Edge 0 X 1 0 X 1 0 8 CR7 X 1 0 X 1 Rising Clock edge Reserved 001 CR2-CR0 Burst Length XXX 010 111 4 Words 8 Words Continuous 7 6 to 4 3 to 1 CR6 CR5-CR3 Sequential Falling Clock edge R valid Low one cycle before valid Clock edge Interleaved Y-Latency = 2 R valid Low during valid Clock edge X-Latency = 6, 6-1-1-1, 6-2-2-2 X-Latency = 7, 7-1-1-1, 7-2-2-2 X-Latency = 8, 8-1-1-1, 8-2-2-2 X and Y-Latencies remains as set in CR13-CR11 and CR9 Divides internal clock, X and Y-Latencies multiplied by 2 Y-Latency = 1 Asynchronous Bus Read (default at power-up) Reserved Reserved X-Latency = 4, 4-1-1-1 (use only with Y-Latency = 1)(1) X-Latency = 5, 5-1-1-1, 5-2-2-2 Value 0 CR15 Read Select Description Synchronous Burst Read
11
CR10
9
CR8
Note: 1. 4 - 2 - 2 - 2 (represents X-Y-Y-Y) is not allowed. 2. X latencies can be calculated as: (t AVQV - tLLKH + tQVKH) + tSYSTEM MARGIN < (X -1) tK. (X is an integer number from 4 to 8 and tK is the clock period). 3. Y latencies can be calculated as: tKHQV + tSYSTEM MARGIN + tQVKH < Y tK. 4. tSYSTEM MARGIN is the time margin required for the calculation.
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Table 4. Burst Type Definition
Starting Address 0 1 2 3 4 5 6 7 8 x4 Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 - - - - - x4 Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 - - - - - x8 Sequential 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 - x8 Interleaved 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 - Continuous 0-1-2-3-4-5-6-7-8-9-10.. 1-2-3-4-5-6-7-8-9-10-11.. 2-3-4-5-6-7-8-9-10-11-12.. 3-4-5-6-7-8-9-10-11-12-13.. 4-5-6-7-8-9-10-11-2-13-14.. 5-6-7-8-9-10-11-12-13-14.. 6-7-8-9-10-11-12-13-14-15.. 7-8-9-10-11-12-13-14-15-16.. 8-9-10-11-12-13-14-15-16-17..
Figure 6. Burst Configuration X-1-1-1
0 K 1 2 3 4 5 6 7 8 9
ADD
VALID
L
DQ
4-1-1-1
VALID
VALID
VALID
VALID
VALID
VALID
DQ
5-1-1-1
VALID
VALID
VALID
VALID
VALID
DQ DQ DQ
6-1-1-1
VALID
VALID VALID
VALID
VALID VALID VALID
7-1-1-1
VALID VALID
8-1-1-1
AI05512
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Figure 7. Burst Configuration X-2-2-2
0 K 1 2 3 4 5 6 7 8 9
ADD
VALID
L
DQ
NV
5-2-2-2
VALID
NV
VALID
NV
VALID
DQ DQ DQ
6-2-2-2
NV
VALID NV
NV
VALID NV
NV VALID NV
7-2-2-2
VALID NV
8-2-2-2
VALID
NV=NOT VALID
AI05513
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COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. The Commands are summarized in Table 5, Commands. Refer to Table 5 in conjunction with the text descriptions below. After power-up or a Reset operation the memory enters Read mode. Synchronous Read operations and Latch Controlled Bus Read operations can only be used to read the memory array. The Electronic Signature, CFI or Status Register will be read in asynchronous mode or single synchronous burst mode. Once the memory returns to Read Memory Array mode the bus will resume the setting in the Configuration Register automatically. Read Memory Array Command. The Read Memory Array command returns the memory to Read mode. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read commands will access the memory array. While the Program/Erase Controller is executing a Program, Erase, Block Protect, Blocks Unprotect or Protection Register Program operation the memory will not accept the Read Memory Array command until the operation completes. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code, the Device Code, the Block Protection Status, the Configuration Register and the Protection Register. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code, the Device Code, the Block Protection Status, the Configuration Register or the Protection Register until another command is issued. Refer to Table 7, Read Electronic Signature, Table 8, Read Protection Register and Figure 8, Protection Register Memory Map for information on the addresses. Read Query Command. The Read Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. One Bus Write cycle is required to issue the Read Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. See Appendix B, Tables 26, 27, 28, 29, 30 and 31 for details on the information contained in the Common Flash Interface (CFI) memory area. Read Status Register Command. The Read Status Register command is used to read the Status
Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. The Status Register information is present on the output data bus (DQ1-DQ7) when both Chip Enable and Output Enable are low, V IL. See the section on the Status Register and Table 10 for details on the definitions of the Status Register bits Clear Status Register Command. The Clear Status Register command can be used to reset bits SR1, SR3, SR4 and SR5 in the Status Register to `0'. One Bus Write is required to issue the Clear Status Register command. The bits in the Status Register are sticky and do not automatically return to `0' when a new Write to Buffer and Program, Erase, Block Protect, Block Unprotect or Protection Register Program command is issued. If any error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program, Erase or Resume command. Block Erase Command. The Block Erase command can be used to erase a block. It sets all of the bits in the block to `1'. All previous data in the block is lost. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Erase operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Erase times are given in Table 9. See Appendix C, Figure 25, Block Erase Flowchart and Pseudo Code, for a suggested flowchart on using the Block Erase command. Word Program Command. The Word Program command is used to program a single word in the memory array. Two Bus Write operations are required to issue the command; the first write cycle sets up the Word Program command, the second write cycle latches the address and data to be programmed in the internal state machine and starts the Program/Erase Controller.
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If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. The block must be unprotected using the Blocks Unprotect command. Write to Buffer and Program Command. The Write to Buffer and Program command is used to program the memory array. Up to 16 Words can be loaded into the Write Buffer and programmed into the memory. Each Write Buffer has the same A5-A21 addresses. Four successive steps are required to issue the command. 1. One Bus Write operation is required to set up the Write to Buffer and Program Command. Issue the set up command with the selected memory Block Address where the program operation should occur (any address in the block where the values will be programmed can be used). Any Bus Read operations will start to output the Status Register after the 1st cycle. 2. Use one Bus Write operation to write the same block address along with the value N on the Data Inputs/Output, where N+1 is the number of Words to be programmed. 3. Use N+1 Bus Write operations to load the address and data for each Word into the Write Buffer. See the constraints on the address combinations listed below. The addresses must have the same A5-A21. 4. Finally, use one Bus Write operation to issue the final cycle to confirm the command and start the Program operation. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will set an error in the Status Register and abort the operation without affecting the data in the memory array. The Status Register should be cleared before re-issuing the command. If the block being programmed is protected an error will be set in the Status Register and the operation will abort without affecting the data in the memory array. The block must be unprotected using the Blocks Unprotect command. See Appendix C, Figure 23, Write to Buffer and Program Flowchart and Pseudo Code, for a suggested flowchart on using the Write to Buffer and Program command. Program/Erase Suspend Command. The Program/Erase Suspend command is used to pause a Word Program, Write to Buffer and Program or Erase operation. The command will only be accepted during a Program or an Erase operation. It can be issued at any time during an Erase operation but will only be accepted during a Word Program or Write to Buffer and Program command if the Program/Erase Controller is running. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit (SR7) to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/ Erase Controller has paused. After the Program/ Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/ Erase Controller pausing it is possible for the operation to complete. Once the Program/Erase Controller Status bit (SR7) indicates that the Program/Erase Controller is no longer active, the Program Suspend Status bit (SR2) or the Erase Suspend Status bit (SR6) can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 9. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature, Read Query and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Erase then the Write to Buffer and Program, and the Program Suspend commands will also be accepted. When a program operation is completed inside a Block Erase Suspend the Read Memory Array command must be issued to reset the device in Read mode, then the Erase Resume command can be issued to complete the whole sequence. Only the blocks not being erased may be read or programmed correctly. See Appendix C, Figure 24, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 26, Erase Suspend & Resume Flowchart and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend operation has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations read the Status Register. Set Configuration Register Command. The Set Configuration Register command is used to write a new value to the Burst Configuration Control Register which defines the burst length, type, X and Y latencies, Synchronous/Asynchronous
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Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command. Once the command is issued the memory returns to Read mode as if a Read Memory Array command had been issued. The value for the Configuration Register is presented on A1-A16. CR0 is on A1, CR1 on A2, etc.; the other address bits are ignored. Block Protect Command. The Block Protect command is used to protect a block and prevent Program or Erase operations from changing the data in it. Two Bus Write cycles are required to issue the Block Protect command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Protect operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 9. The Block Protection bits are non-volatile, once set they remain set through reset and powerdown/power-up. They are cleared by a Blocks Unprotect command. See Appendix C, Figure 27, Block Protect Flowchart and Pseudo Code, for a suggested flowchart on using the Block Protect command. Blocks Unprotect Command. The Blocks Unprotect command is used to unprotect all of the blocks. Two Bus Write cycles are required to issue the Blocks Unprotect command; the second Bus Write cycle starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Block Unprotect operation the memory will only accept the Read Status Register command. All other commands will be ignored. Typical Block Protection times are given in Table 9. See Appendix C, Figure 28, Block Unprotect Flowchart and Pseudo Code, for a suggested flowchart on using the Block Unprotect command. Protection Register Program Command. The Protection Register Program command is used to Program the 64 bit user segment of the Protection Register. The segment is programmed 16 bits at a time. Two write cycles are required to issue the Protection Register Program command. s The first bus cycle sets up the Protection Register Program command. s The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The user-programmable segment can be locked by programming bit 1 of the Protection Register Lock location to `0' (see Table 8). Bit 0 of the Protection Register Lock location locks the factory programmed segment and is programmed to `0' in the factory. The locking of the Protection Register is not reversible, once the lock bits are programmed no further changes can be made to the values stored in the Protection Register, see Figure 8, Protection Register Memory Map. Attempting to program a previously protected Protection Register will result in a Status Register error. The Protection Register Program cannot be suspended. See Appendix C, Figure 29, Protection Register Program Flowchart and Pseudo Code, for the flowchart for using the Protection Register Program command. Configure STS Command. The Configure STS command is used to configure the Status/(Ready/Busy) pin. After power-up or reset the STS pin is configured in Ready/Busy mode. The pin can be configured in Status mode using the Configure STS command (refer to Status/(Ready/Busy) section for more details. Two write cycles are required to issue the Configure STS command. s The first bus cycle sets up the Configure STS command. s The second specifies one of the four possible configurations (refer to Table 6, Configuration Codes): - Ready/Busy mode - Pulse on Erase complete mode - Pulse on Program complete mode - Pulse on Erase or Program complete mode The device will not accept the Configure STS command while the Program/Erase controller is busy or during Program/Erase Suspend. When STS pin is pulsing it remains Low for a typical time of 250ns. Any invalid Configuration Code will set an error in the Status Register.
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Table 5. Commands
Command Cycles Bus Operations 1st Cycle Op. Write Write Write Write Write Write Write Addr. Data X X X X X X X BA X X X X X X X FFh 90h 70h 98h 50h 20h 40h 10h E8h B0h D0h 60h 60h 60h C0h B8h Write Write Write Write Write BCR BA X PRA X 03h 01h D0h PRD CC Write Write Write BA PA BA D0 PD N Write PA PD Write X D0h Op. Read Read Read Read 2nd Cycle Addr. RA IDA(3) X QA(4) Data RD IDD(3) SRD QD(4) Subsequent Op. Final
Addr. Data Op. Addr. Data
Read Memory Array Read Electronic Signature Read Status Register Read Query Clear Status Register Block Erase Word Program Write to Buffer and Program Program/Erase Suspend Program/Erase Resume Set Configuration Register Block Protect Blocks Unprotect Protection Register Program Configure STS command
2 2 2 2 1 2 2
4 + N Write 1 1 2 2 2 2 2 Write Write Write Write Write Write Write
Note: 1. X Don't Care; RA Read Address, RD Read Data, IDA Identifier Address, IDD Identifier Data, SRD Status Register Data, PA Program Address; PD Program Data, QA Query Address, QD Query Data, BA Any address in the Block, BCR Configuration Register value, CC Configuration Code. 2. Base Address, refer to Figure 8 and Table 8 for more information. 3. For Identifier addresses and data refer to table 7, Read Electronic Signature. 4. For Query Address and Data refer to Appendix B, CFI.
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Table 6. Configuration Codes
Configuration Code DQ1 DQ2 Mode STS Pin VOL during P/E operations Hi-Z when the memory is ready Description The STS pin is Low during Program and Erase operations and high impedance when the memory is ready for any Read, Program or Erase operation. Supplies a system interrupt pulse at the end of a Block Erase operation. Pulse Low then High when operation completed(2) Supplies a system interrupt pulse at the end of a Program operation. Supplies a system interrupt pulse at the end of a Block Erase or Program operation.
00h
0
0
Ready/Busy
01h
0
1
Pulse on Erase complete Pulse on Program complete Pulse on Erase or Program complete
02h
1
0
03h
1
1
Note: 1. DQ2-DQ7 are reserved 2. When STS pin is pulsing it remains Low for a typical time of 250ns.
Table 7. Read Electronic Signature
Code Manufacturer Code Device Code Block Protection Status Configuration Register Protection Register Address (A21-A1) 000000h 000001h SBA+02h 000005h 000080h
(2)
Data (DQ15-DQ0) 0020h 8822h 0000h (Block Unprotected) 0001h (Block Protected) BCR PRD
Note: 1. SBA is the Start Base Address of each block, BCR is Configuration Register data, PRD is Protection Register Data. 2. Base Address, refer to Figure 8 and Table 8 for more information.
Table 8. Read Protection Register
Word Lock 0 1 2 3 4 5 6 7 Use Factory, User Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) Factory (Unique ID) User User User User A8 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 1 A3 0 0 0 0 1 1 1 1 0 A2 0 0 1 1 0 0 1 1 0 A1 0 1 0 1 0 1 0 1 0
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Figure 8. Protection Register Memory Map
WORD ADDRESS 88h User Programmable 85h 84h Unique device number 81h 80h Protection Register Lock 1 0
AI05501
Table 9. Program, Erase Times and Program Erase Endurance Cycles
M58LW032C Parameters Min Block (1Mb) Erase Chip Program (Write to Buffer) Chip Erase Time Program Write Buffer Word/Byte Program Time (Word/Byte Program command) Program Suspend Latency Time Erase Suspend Latency Time Block Protect Time Blocks Unprotect Time Program/Erase Cycles (per block) Data Retention
Note: 1. 2. 3. 4. 5.
Typ(1,2) 1.2 24 37 192 (3) 16 1 1 18 0.75
Max(2) 4.8(4) 72(4) 110 (4) 576 (4) 48 (4) 20 (5) 25 (5) 30 (5) 1.2 (5)
Unit s s s s s s s s s cycles years
100,000 20
Typical values measured at room temperature and nominal voltages. Sampled, but not 100% tested. Effective byte programming time 6s, effective word programming time 12s. Maximum value measured at worst case conditions for both temperature and VDD after 100,000 program/erase cycles. Maximum value measured at worst case conditions for both temperature and VDD.
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STATUS REGISTER The Status Register provides information on the current or previous Program, Erase, Block Protect or Blocks Unprotect operation. The various bits in the Status Register convey information and errors on the operation. They are output on DQ7-DQ0. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase, Block Protect, Blocks Unprotect and Program/Erase Resume commands. The Status Register can be read from any address. The Status Register can only be read using Asynchronous Bus Read or Single Synchronous Read operations. Once the memory returns to Read Memory Array mode the bus will resume the setting in the Configuration Register automatically. The contents of the Status Register can be updated during an Erase or Program operation by toggling the Output Enable pin or by dis-activating (Chip Enable, VIH) and then reactivating (Chip Enable and Output Enable, V IL) the device. Status Register bits SR5, SR4, SR3 and SR1 are associated with various error conditions and can only be reset with the Clear Status Register command. The Status Register bits are summarized in Table 10, Status Register Bits. Refer to Table 10 in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is Low, VOL, the Program/Erase Controller is active and all other Status Register bits are High Impedance; when the bit is High, V OH, the Program/Erase Controller is inactive. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, Block Protect and Blocks Unprotect operations the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status and Block Protection Status bits should be tested for errors. Erase Suspend Status Bit ( SR6). The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller
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inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is Low, V OL, the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block has erased correctly or that all blocks have been unprotected successfully. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). When the Erase Status bit is Low, V OL, the memory has successfully verified that the block has erased correctly or all blocks have been unprotected successfully. When the Erase Status bit is High, VOH, the erase operation has failed. Depending on the cause of the failure other Status Register bits may also be set to High, VOH. s If only the Erase Status bit (SR5) is set High, VOH, then the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly or that all the blocks have been unprotected successfully. s If the failure is due to an erase or blocks unprotect with VPEN low, VOL, then VPEN Status bit (SR3) is also set High, VOH. s If the failure is due to an erase on a protected block then Block Protection Status bit (SR1) is also set High, VOH. s If the failure is due to a program or erase incorrect command sequence then Program Status bit (SR4) is also set High, VOH. Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4). The Program Status bit is used to identify a Program or Block Protect failure. The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). When the Program Status bit is Low, V OL, the memory has successfully verified that the Write Buffer has programmed correctly or the block is protected. When the Program Status bit is High, VOH, the program or block protect operation has
M58LW032C
failed. Depending on the cause of the failure other Status Register bits may also be set to High, VOH. s If only the Program Status bit (SR4) is set High, VOH, then the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the Write Buffer has programmed correctly or that the Block is protected. s If the failure is due to a program or block protect with VPEN low, VOL, then VPEN Status bit (SR3) is also set High, VOH. s If the failure is due to a program on a protected block then Block Protection Status bit (SR1) is also set High, VOH. s If the failure is due to a program or erase incorrect command sequence then Erase Status bit (SR5) is also set High, VOH. Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. VPEN Status Bit (SR3). The VPEN Status bit can be used to identify if a Program, Erase, Block Protection or Block Unprotection operation has been attempted when VPEN is Low, VIL. When the VPEN Status bit is Low, VOL, no Program, Erase, Block Protection or Block Unprotection operations have been attempted with VPEN Low, VIL, since the last Clear Status Register command, or hardware reset. When the VPEN Status bit is High, VOH, a Program, Erase, Block Protection or Block Unprotection operation has been attempted with VPEN Low, VIL. Once set High, the VPEN Status bit can only be reset by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program, Erase, Block Protection or Block Unprotection command is issued, otherwise the new command will appear to fail. Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is Low, VOL, the Program/Erase Controller is active or has completed its operation; when the bit is High, VOH, a Program/Erase Suspend command has been issued and the memory is waiting for a Program/ Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1). The Block Protection Status bit can be used to identify if a Program or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is Low, V OL, no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is High, VOH, a Program (Program Status bit SR4 set High) or Erase (Erase Status bit SR5 set High) operation has been attempted on a protected block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Reserved (SR0). SR0 of the Status Register is reserved. Its value should be masked.
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Table 10. Status Register Bits
OPERATION Program/Erase Controller active Write Buffer not ready Write Buffer ready Write Buffer ready in Erase Suspend Program suspended Program suspended in Erase Suspend Program/Block Protect completed successfully Program completed successfully in Erase Suspend Program/Block protect failure due to incorrect command sequence Program failure due to incorrect command sequence in Erase Suspend Program/Block Protect failure due to SR7 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 SR6 SR5 SR4 SR3 SR2 SR1 RB VOL VOL 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Result (Hex) N/A N/A 80h C0h 84h C4h 80h C0h B0h F0h 98h D8h 92h D2h 90h D0h C0h 80h B0h A8h A2h A0h
Hi-Z Hi-Z
VPEN error
Program failure due to VPEN error in Erase Suspend Program failure due to Block Protection Program failure due to Block Protection in Erase Suspend Program/Block Protect failure due to cell failure Program failure due to cell failure in Erase Suspend Erase Suspended Erase/Blocks Unprotect completed successfully Erase/Blocks Unprotect failure due to incorrect command sequence Erase/Blocks Unprotect failure due to VPEN error Erase failure due to Block Protection Erase/Blocks Unprotect failure due to failed cells in Block
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MAXIMUM RATING Stressing the device above the ratings listed in Table 11, Absolute Maximum Ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 11. Absolute Maximum Ratings
Value Symbol TBIAS TSTG VIO VDD, VDDQ Parameter Min Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage -40 -55 -0.6 -0.6 Max 125 150 VDDQ +0.6 5.0 C C V V Unit
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
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DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measure-
ment Conditions summarized in Table 12, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 12. Operating and AC Measurement Conditions
M58LW032C Units Parameter Min Supply Voltage (VDD) Input/Output Supply Voltage (VDDQ) Ambient Temperature (TA) Load Capacitance (CL) Clock Rise and Fall Times Input Rise and Fall Times Input Pulses Voltages Input and Output Timing Ref. Voltages 0 to VDDQ 0.5 VDDQ Grade 1 Grade 6 2.7 1.8 0 -40 30 3 4 90, 110 Max 3.6 VDD 70 85 V V C C pF ns ns V V
Figure 9. AC Measurement Input Output Waveform
Figure 10. AC Measurement Load Circuit
1.3V
1N914 VDDQ VDD VDDQ 0.5 VDDQ 0V
AI00610
3.3k DEVICE UNDER TEST CL 0.1F 0.1F CL includes JIG capacitance
AI03459
DQS
Table 13. Capacitance
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Typ 6 8 Max 8 12 Unit pF pF
Note: 1. TA = 25C, f = 1 MHz 2. Sampled only, not 100% tested.
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Table 14. DC Characteristics
Symbol ILI ILO IDD IDDB IDD1 IDD5 IDD2 IDD3 IDD4 VIL VIH VOL VOH VLKO Parameter Input Leakage Current Output Leakage Current Supply Current (Random Read) Supply Current (Burst Read) Supply Current (Standby) Supply Current (Auto Low-Power) Supply Current (Reset/Power-Down) Supply Current (Program or Erase, Block Protect, Block Unprotect) Supply Current (Erase/Program Suspend) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VDD Supply Voltage (Erase and Program lockout) IOL = 100A IOH = -100A VDDQ -0.2 2 Test Condition 0V VIN VDDQ 0V VOUT VDDQ E = VIL, G = VIH, fadd = 6MHz E = VIL, G = VIH, fclock = 50MHz E = VIH, RP = VIH E = VIL, RP = VIH RP = VIL Program or Erase operation in progress E = VIH -0.5 VDDQ x 0.7 Min Max 1 5 20 30 40 40 40 30 40 VDDQ x 0.3 VDDQ + 0.5 0.2 Unit A A mA mA A A A mA A V V V V V
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Figure 11. Asynchronous Bus Read AC Waveforms
tAVAV A1-A21 tELQV tELQX E tAXQX VALID
L tGLQV tGLQX G tAVQV tGHQZ tGHQX DQ0-DQ15 OUTPUT tEHQZ tEHQX
AI06255
Note: Asynchronous Read CR15 = 1
Table 15. Asynchronous Bus Read AC Characteristics.
M58LW032C Symbol tAVAV tAVQV tELQX tELQV tGLQX tGLQV tEHQX tGHQX tAXQX tEHQZ tGHQZ Parameter 90 Address Valid to Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Output Enable High to Output Transition Address Transition to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Min Max Min Max Min Max Min Min Min Max Max 90 90 0 90 0 25 0 0 0 25 20 110 110 110 0 110 0 25 0 0 0 25 20 ns ns ns ns ns ns ns ns ns ns ns Unit
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Figure 12. Asynchronous Latch Controlled Bus Read AC Waveforms
A1-A21 tAVLH tAVLL L tLHLL tLLLH tELLH tELLL E tGLQV tGLQX G tLLQX tLLQV DQ0-DQ15 OUTPUT
AI06256b
VALID tLHAX
tEHLX
tEHQZ tEHQX
tGHQZ tGHQX
Note: Asynchronous Read CR15 = 1
Table 16. Asynchronous Latch Controlled Bus Read AC Characteristics
M58LW032C Symbol tAVLL tAVLH tLHLL tLLLH tELLL tELLH tLLQX tLLQV tLHAX tGLQX tGLQV tEHLX Parameter 90 Address Valid to Latch Enable Low Address Valid to Latch Enable High Latch Enable High to Latch Enable Low Latch Enable Low to Latch Enable High Chip Enable Low to Latch Enable Low Chip Enable Low to Latch Enable High Latch Enable Low to Output Transition Latch Enable Low to Output Valid Latch Enable High to Address Transition Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Latch Enable Transition Min Min Min Min Min Min Min Min Min Min Max Min 0 10 10 10 0 10 0 90 6 0 25 0 110 0 10 10 10 0 10 0 110 6 0 25 0 ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
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Figure 13. Asynchronous Page Read AC Waveforms
A1-A2 VALID VALID
A3-A21 tAVQV tELQV tELQX E L tGLQV tGLQX G
VALID
tAXQX
tAVQV1 tAXQX1
tEHQZ tEHQX
tGHQZ tGHQX DQ0-DQ15 OUTPUT OUTPUT
AI06257
Note: Asynchronous Read CR15 = 1
Table 17. Asynchronous Page Read AC Characteristics
M58LW032C Symbol tAXQX1 tAVQV1 Parameter 90, 110 Address Transition to Output Transition Address Valid to Output Valid Min Max 6 25 ns ns Unit
Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
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Figure 14. Asynchronous Write AC Waveform, Write Enable Controlled
A1-A21 tAVWH E VALID tWHAX
L tELWL G tGHWL W tDVWH DQ0-DQ15 INPUT tWHDX RB tVPHWH VPEN
AI06258
tWHEH
tWLWH
tWHWL
tWHGL
tWHBL
Figure 15. Asynchronous Latch Controlled Write AC Waveform, Write Enable Controlled
A1-A21 tAVLH VALID tLHAX
L
tELLL
tLLLH tWLLH tLHWH
tLHGL
E tELWL G tGHWL W tDVWH DQ0-DQ15 INPUT tWHDX RB tVPHWH VPEN
AI06259
tWHEH
tWLWH
tWHWL
tWHGL
tWHBL
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Table 18. Asynchronous Write and Latch Controlled Write AC Characteristics, Write Enable Controlled.
M58LW032C Symbol tAVLH tAVWH tDVWH tELWL tELLL tLHAX tLHGL tLHWH tLLLH tLLWH tVPHWH tWHAX tWHBL tWHDX tWHEH tGHWL tWHGL tWHWL tWLWH tWLLH Parameter 90, 110 Address Valid to Latch Enable High Address Valid to Write Enable High Data Input Valid to Write Enable High Chip Enable Low to Write Enable Low Chip Enable Low to Latch Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable High to Write Enable High Latch Enable low to Latch Enable High Latch Enable Low to Write Enable High Program/Erase Enable High to Write Enable High Write Enable High to Address Transition Write Enable High to Ready/Busy low Write Enable High to Input Transition Write Enable High to Chip Enable High Output Enable High to Write Enable Low Write Enable High to Output Enable Low Write Enable High to Write Enable Low Write Enable Low to Write Enable High Write Enable Low to Latch Enable High Min Min Min Min Min Min Min Min Min Min Min Min Max Min Min Min Min Min Min Min 10 50 50 0 0 6 95 0 10 50 0 0 500 0 0 20 35 30 70 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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Figure 16. Asynchronous Write AC Waveforms, Chip Enable Controlled
A1-A21 tAVEH W tWLEL G tGHEL E L
VALID tEHAX
tEHWH
tELEH
tEHEL
tEHGL
tDVEH DQ0-DQ15 INPUT tEHDX RB tVPHEH VPEN
AI06260
tEHBL
Figure 17. Asynchronous Latch Controlled Write AC Waveforms, Chip Enable Controlled
A1-A21 tAVLH tAVEH L tWLLL tLLLH tELLH W tWLEL G tGHEL E tDVEH DQ0-DQ15 INPUT tEHDX RB tVPHEH VPEN
AI06261
VALID tLHAX tEHAX
tLHEH tLHGL
tEHWH
tELEH
tEHEL
tEHGL
tEHBL
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Table 19. Asynchronous Write and Latch Controlled Write AC Characteristics, Chip Enable Controlled
M58LW032C Symbol tAVLH tAVEH tDVEH tEHAX tEHBL tEHDX tEHWH tEHGL tEHEL tELEH tELLH tGHEL tLHAX tLHGL tLHEH tLLLH tLLEH tVPHEH tWLEL tWLLL Parameter 90, 110 Address Valid to Latch Enable High Address Valid to Chip Enable High Data Input Valid to Chip Enable High Chip Enable High to Address Transition Chip Enable High to Ready/Busy low Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Output Enable Low Chip Enable High to Chip Enable Low Chip Enable Low to Chip Enable High Chip Enable Low to Latch Enable High Output Enable High to Chip Enable Low Latch Enable High to Address Transition Latch Enable High to Output Enable Low Latch Enable High to Chip Enable High Latch Enable low to Latch Enable High Latch Enable Low to Chip Enable High Program/Erase Enable High to Chip Enable High Write Enable Low to Chip Enable Low Write Enable Low to Latch Enable Low Min Min Min Min Max Min Min Min Min Min Min Min Min Min Min Min Min Min Min Min 10 50 50 0 500 0 0 35 30 70 10 20 6 35 0 10 50 0 0 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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0 X+2Y+1
1
2
X-1
X
X+Y
X+2Y
X+2Y+2
K tKHAX
tKHLL
Note: Valid Clock Edge = Rising (CR6 = 1)
A1-A21 tLHAX
VALID
tLLKH
tLLLH
Figure 18. Synchronous Burst Read AC Waveform
L
tAVKH tAVLH tELKH tELLH
tEHQZ tEHQX
E tGLKH tGHQZ tGHQX
G
tKHQV
tKHQX
tQVKH Q1 Q2 Q3
DQ0-DQ15
M58LW032C
AI06262
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Figure 19. Synchronous Burst Read - Continuous - Valid Data Ready Output
K
Output (2)
V
V
V
NV tRLKH
NV
V
V
R
(3)
AI05510
Note: 1. Valid Data Ready = Valid Low during valid clock edge (CR8 = 0) 2. V= Valid output, NV= Not Valid output. 3. R is an open drain output with an internal pull up resistor of 1M. Depending on the Valid Data Ready pin capacitance load an external pull up resistor must be chosen according to the system clock period.
Table 20. Synchronous Burst Read AC Characteristics
M58LW032C Symbol tAVKH tAVLH tELKH tELLH tGLKH tKHAX tKHLL tKHLH tKHQX tLLKH tLLLH tKHQV tQVKH tRLKH Parameter 90, 110 Address Valid to Active Clock Edge Address Valid to Latch Enable High Chip Enable Low to Active Clock Edge Chip Enable Low to Latch Enable High Output Enable Low to Valid Clock Edge Valid Clock Edge to Address Transition Valid Clock Edge to Latch Enable Low Valid Clock Edge to Latch Enable High Valid Clock Edge to Output Transition Latch Enable Low to Valid Clock Edge Latch Enable Low to Latch Enable High Valid Clock Edge to Output Valid Output Valid to Active Clock Edge Valid Data Ready Low to Valid Clock Edge Min Min Min Min Min Min Min Min Min Min Min Max Min Min 7 10 10 10 20 5 0 0 3 6 7 15 5 5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Note: For other timings see Table 15, Asynchronous Bus Read Characteristics.
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Figure 20. Reset, Power-Down and Power-up AC Waveform
W
E, G
DQ0-DQ15 tPHQV
RB tPLRH RP tVDHPH VDD, VDDQ Power-Up and Reset Reset during Program or Erase
AI05521
tPLPH
Table 21. Reset, Power-Down and Power-up AC Characteristics
M58LW032C Symbol tPHQV tPLPH tPLRH tVDHPH Parameter 90 Reset/Power-Down High to Data Valid Reset/Power-Down Low to Reset/Power-Down High Reset/Power-Down Low to Ready High Supply Voltages High to Reset/Power-Down High Max Min Max Min 130 100 30 0 110 150 100 30 0 ns ns s s Unit
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PACKAGE MECHANICAL Figure 21. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Outline
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note: Drawing is not to scale.
Table 22. TSOP56 - 56 lead Plastic Thin Small Outline, 14 x 20 mm, Package Mechanical Data
mm Symbol Typ A A1 A2 B C D D1 E e L N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 13.90 - 0.50 0 56 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 14.10 - 0.70 5 0.0197 0.0020 0.0374 0.0067 0.0039 0.7795 0.7205 0.5472 - 0.0197 0 56 0.0039 Typ Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.7953 0.7283 0.5551 - 0.0276 5 inches
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Figure 22. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Outline
D FD FE D1 SD
E
E1
SE
ddd BALL "A1"
A
e
b A1
A2
BGA-Z23
Note: Drawing is not to scale.
Table 23. TBGA64 10x13mm - 8x8 ball array, 1mm pitch, Package Mechanical Data
millimeters Symbol Typ A A1 A2 b D D1 ddd e E E1 FD FE SD SE 1.000 13.000 7.000 1.500 3.000 0.500 0.500 - 12.900 - - - - - 10.000 7.000 0.400 9.900 - 0.300 0.200 Min Max 1.200 0.350 0.850 0.500 10.100 - 0.100 - 13.100 - - - - - 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 - 0.5079 - - - - - 0.3937 0.2756 0.0157 0.3898 - 0.0118 0.0079 Typ Min Max 0.0472 0.0138 0.0335 0.0197 0.3976 - 0.0039 - 0.5157 - - - - - inches
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PART NUMBERING Table 24. Ordering Information Scheme
Example: Device Type M58 Architecture L = Page Mode, Burst Operating Voltage W = VDD = 2.7V to 3.6V; VDDQ = 1.8 to VDD Device Function 032C = 32 Mbit (x16), Uniform Block Speed 90 = 90ns 110 = 110ns Package N = TSOP56: 14 x 20 mm ZA = TBGA64: 10 x 13mm, 1mm pitch Temperature Range 1 = 0 to 70 C 6 = -40 to 85 C Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-free Package, Standard Packing F = Lead-free Package, Tape & Reel Packing M58LW032C 110 N 1 T
Note: Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
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APPENDIX A. BLOCK ADDRESS TABLE Table 25. Block Addresses
Block Number 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Address Range (x16 Bus Width) 1F0000h-1FFFFFh 1E0000h-1EFFFFh 1D0000h-1DFFFFh 1C0000h-1CFFFFh 1B0000h-1BFFFFh 1A0000h-1AFFFFh 190000h-19FFFFh 180000h-18FFFFh 170000h-17FFFFh 160000h-16FFFFh 150000h-15FFFFh 140000h-14FFFFh 130000h-13FFFFh 120000h-12FFFFh 110000h-11FFFFh 100000h-10FFFFh 0F0000h-0FFFFFh 0E0000h-0EFFFFh 0D0000h-0DFFFFh 0C0000h-0CFFFFh 0B0000h-0BFFFFh 0A0000h-0AFFFFh 090000h-09FFFFh 080000h-08FFFFh 070000h-07FFFFh 060000h-06FFFFh 050000h-05FFFFh 040000h-04FFFFh 030000h-03FFFFh 020000h-02FFFFh 010000h-01FFFFh 000000h-00FFFFh
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APPENDIX B. COMMON FLASH INTERFACE - CFI The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the deTable 26. Query Structure Overview
Offset 00h 01h 10h 1Bh 27h P(h)(1) A(h)(2) (SBA+02)h CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query Table Alternate Algorithm-specific Extended Query Table Block Status Register Sub-section Name Description Manufacturer Code Device Code Command set ID and algorithm data offset Device timing and voltage information Flash memory layout Additional information specific to the Primary Algorithm (optional) Additional information specific to the Alternate Algorithm (optional) Block-related Information
vice, enabling the software to upgrade itself when necessary. When the CFI Query Command (RCFI) is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 26, 27, 28, 29, 30 and 31 show the addresses used to retrieve the data.
Note: 1. Offset 15h defines P which points to the Primary Algorithm Extended Query Address Table. 2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table. 3. SBA is the Start Base Address for each block.
Table 27. CFI - Query Address and Data Output
Address A21-A1 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah(2) 51h 52h 59h 01h 00h 31h Primary algorithm extended Query Address Table: P(h) 00h 00h 00h 00h Alternate Algorithm Extended Query address Table 00h Alternate Vendor: Command Set and Control Interface ID Code Data "Q" "R" "Y" Query ASCII String Instruction 51h; "Q" 52h; "R" 59h; "Y"
Primary Vendor: Command Set and Control Interface ID Code
Note: 1. Query Data are always presented on DQ7-DQ0. DQ15-DQ8 are set to '0'. 2. Offset 19h defines A which points to the Alternate Algorithm Extended Query Address Table.
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Table 28. CFI - Device Voltage and Timing Specification
Address A21-A1 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 27h (1) 36h (1) 00h (2) 00h (2) 04h 08h 0Ah 00h (3) 04h 04h 04h 00h (3) VDD Min, 2.7V VDD max, 3.6V VPP min - Not Available VPP max - Not Available 2n s typical time-out for Word, DWord prog - Not Available 2n s, typical time-out for max buffer write 2n ms, typical time-out for Erase Block 2n ms, typical time-out for chip erase - Not Available 2n x typical for Word Dword time-out max - Not Available 2n x typical for buffer write time-out max 2n x typical for individual block erase time-out maximum 2n x typical for chip erase max time-out - Not Available Description
Note: 1. Bits are coded in Binary Code Decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV. 2. Bit7 to bit4 are coded in Hexadecimal and scaled in Volts while bit3 to bit0 are in Binary Code Decimal and scaled in 100mV. 3. Not supported.
Table 29. Device Geometry Definition
Address A21-A1 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h Data 16h 01h 00h 05h 00h 01h 1Fh Number (n-1) of Erase Blocks of identical size; n=64 00h 00h 02h Erase Block Region Information x 256 bytes per Erase block (128K bytes) Description n where 2n is number of bytes memory Size Device Interface Organization Sync./Async. Maximum number of bytes in Write Buffer, 2n Bit7-0 = number of Erase Block Regions in device
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Table 30. Block Status Register
Address A21-A1 bit0 1 (BA+2)h(1) 0 bit1 1 bit7-2
Note: 1. BA specifies the block address location, A21-A17. 2. Not Supported.
Data 0
Selected Block Information Block UnProtected Block Protected Last erase operation ended successfully (2) Last erase operation not ended successfully (2) Reserved for future features
0
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Table 31. Extended Query information
Address offset (P)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h Address A21-A2 31h 32h 33h 34h 35h 36h 37h 38h Data (Hex) x16 Bus Width 50h 52h 49h 31h 31h CEh 01h 00h "P" "R" "I" Major version number Minor version number Optional Feature: (1=yes, 0=no) bit0, Chip Erase Supported (0=no) bit1, Suspend Erase Supported (1=yes) bit2, Suspend Program Supported (1=yes) bit3, Protect/UnProtect Supported (1=yes) bit4, Queue Erase Supported (0=no) bit5, Instant Individual Block locking (0=no) bit6, Protection bits supported (1=yes) bit7, Page Read supported (1=yes) bit8, Synchronous Read supported (1=yes) bits 9 to 31 reserved for future use Function allowed after Suspend: Program allowed after Erase Suspend (1=yes) Bit 7-1 reserved for future use Block Status Register bit0, Block Protect Bit status active (1=yes) bit1, Block Lock-Down Bit status active (not available) bits 2 to 15 reserved for future use VDD OPTIMUM Program/Erase voltage conditions VPP OPTIMUM Program/Erase voltage conditions OTP protection: No. of protection register fields Protection Register's start address, least significant bits Protection Register's start address, most significant bits n where 2n is number of factory reprogrammed bytes n where 2n is number user programmable bytes Page Read: 2n Bytes (n = bits 0-7) Synchronous mode configuration fields n where 2n+1 is the number of Words for the burst Length = 4 n where 2n+1 is the number of Words for the burst Length = 8 Burst Continuous Query ASCII string - Extended Table Description
(P+8)h
39h
00h
(P+9)h (P+A)h (P+B)h (P+C)h (P+D)h (P+E)h (P+F)h (P+10)h (P+11)h (P+12)h (P+13)h (P+14)h (P+15)h (P+16)h (P+17)h
3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h
01h 01h 00h 33h 00h 01h 80h 00h 03h 03h 03h 03h 01h 02h 07h
Note: 1. Bit7 to bit4 are coded in Hexadecimal and scaled in Volt while bit3 to bit0 are in Binary Code Decimal and scaled in mV.
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APPENDIX C. FLOW CHARTS Figure 23. Write to Buffer and Program Flowchart and Pseudo Code
Start Write to Buffer E8h Command, Block Address
Read Status Register NO SR7 = 1 YES Note 1: N+1 is number of Words to be programmed Write N(1), Block Address Try Again Later Write Buffer Data, Start Address NO Write to Buffer Timeout YES
X=0
X=N NO Note 2: Next Program Address must have same A5-A21.
YES
Write Next Buffer Data, Next Program Address(2)
X=X+1
Program Buffer to Flash Confirm D0h
Read Status Register
SR7 = 1 YES Note 3: A full Status Register Check must be done to check the program operation's success. Full Status Register Check(3)
NO
End
AI06263b
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Figure 24. Program Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend Command: - write B0h - write 70h do: - read status register
Read Status Register
SR7 = 1 YES SR2 = 1 YES Write FFh
NO
while SR7 = 1
NO
Program Complete
If SR2 = 0, Program completed
Read Memory Array command: - write FFh - one or more data reads from other blocks
Read data from another block
Write D0h
Write FFh
Program Continues
Read Data
Program Erase Resume Command: - write D0h to resume erasure - if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase Suspend command was not issued).
AI00612b
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Figure 25. Erase Flowchart and Pseudo Code
Start
Write 20h
Write D0h to Block Address
Erase command: - write 20h - write D0h to Block Address (A12-A17) (memory enters read Status Register after the Erase command)
Read Status Register
NO Suspend
YES
do: - read status register - if Program/Erase Suspend command given execute suspend erase loop
SR7 = 1
NO
Suspend Loop
while SR7 = 1
YES SR3 = 0 YES SR4, SR5 = 0 YES SR5 = 0 YES SR1 = 0 YES End
AI00613C
NO
VPEN Invalid Error (1)
If SR3 = 1, VPEN invalid error: - error handler
NO
Command Sequence Error
If SR4, SR5 = 1, Command Sequence error: - error handler
NO
Erase Error (1)
If SR5 = 1, Erase error: - error handler
NO
Erase to Protected Block Error
If SR1 = 1, Erase to Protected Block Error: - error handler
Note: 1. If an error is found, the Status Register must be cleared (Clear Status Register Command) before further Program or Erase operations.
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Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code
Start
Write B0h
Write 70h
Program/Erase Suspend Command: - write B0h - write 70h do: - read status register
Read Status Register
SR7 = 1 YES SR6 = 1 YES Write FFh
NO
while SR7 = 1
NO
Erase Complete
If SR6 = 0, Erase completed
Read Memory Array command: - write FFh - one or more data reads from other blocks
Read data from another block or Program
Write D0h
Write FFh
Erase Continues
Read Data
Program/Erase Resume command: - write D0h to resume the Erase operation - if the Program operation completed then this is not necessary. The device returns to Read mode as normal (as if the Program/Erase suspend was not issued).
AI00615b
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Figure 27. Block Protect Flowchart and Pseudo Code
Start
Write 60h Block Address
Block Protect Command - write 60h, Block Adress - write 01h, Block Adress
Write 01h Block Address
Read Status Register
do: - read status register
SR7 = 1
NO
while SR7 = 1
YES YES VPEN Invalid Error If SR3 = 1, VPEN Invalid Error
SR3 = 1 NO
YES SR4, SR5 = 1,1 NO YES SR4 = 1 NO
Invalid Command Sequence Error
If SR4 = 1, SR5 = 1 Invalid Command Sequence Error
Block Protect Error
If SR4 = 1, Block Protect Error
Write FFh
Read Memory Array Command: - write FFh
Block Protect Sucessful
AI06157b
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Figure 28. Blocks Unprotect Flowchart and Pseudo Code
Start
Write 60h
Blocks Unprotect Command - write 60h, Block Adress - write D0h, Block Adress
Write D0h
Read Status Register
do: - read status register
SR7 = 1
NO
while SR7 = 1
YES YES
SR3 = 1 NO
VPEN Invalid Error
If SR3 = 1, VPEN Invalid Error
YES SR4, SR5 = 1,1 NO YES SR5 = 1 NO
Invalid Command Sequence Error
If SR4 = 1, SR5 = 1 Invalid Command Sequence Error
Blocks Unprotect Error
If SR5 = 1, Blocks Unprotect Error
Write FFh
Read Memory Array Command: - write FFh
Blocks Unprotect Sucessful
AI06158b
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Figure 29. Protection Register Program Flowchart and Pseudo Code
Start
Write C0h
Write PR Address, PR Data
Protection Register Program Command - write C0h - write Protection Register Address, Protection Register Data
Read Status Register
do: - read status register
SR7 = 1
NO
while SR7 = 1
YES YES SR3, SR4 = 1,1 NO YES SR1, SR4 = 0,1 NO YES SR1, SR4 = 1,1 NO If SR3 = 1, SR4 = 1 VPEN Invalid Error
VPEN Invalid Error
Protection Register Program Error
If SR1 = 0, SR4 = 1 Protection Register Program Error
Protection Register Program Error
If SR1 = 1, SR4 = 1 Program Error due to Protection Register Protection
Write FFh
Read Memory Array Command: - write FFh
PR Program Sucessful
AI06159b
Note: PR = Protection Register
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Figure 30. Command Interface and Program Erase Controller Flowchart (a)
WAIT FOR COMMAND WRITE
90h YES READ SIGNATURE
NO
98h YES CFI QUERY
NO
70h YES READ STATUS
NO
50h YES CLEAR STATUS
NO
READ ARRAY
E8h YES PROGRAM BUFFER LOAD
NO
20h(1) YES ERASE SET-UP
NO
FFh YES
NO
NO
D0h YES C A NO
PROGRAM COMMAND ERROR
D0h YES
ERASE COMMAND ERROR
B Note 1. The Erase command (20h) can only be issued if the flash is not already in Erase Suspend.
AI03618
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Figure 31. Command Interface and Program Erase Controller Flowchart (b)
B A
ERASE
(READ STATUS)
READ STATUS
YES
Program/Erase Controller READY Status bit in the Status Register ? NO
READ ARRAY YES FFh NO
B0h YES
NO
READ STATUS ERASE SUSPEND
NO ERASE SUSPENDED YES
READY ? NO
WAIT FOR COMMAND WRITE
YES
READ STATUS
READ STATUS
YES
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
PROGRAM BUFFER LOAD
YES
E8h
NO PROGRAM COMMAND ERROR NO D0h D0h NO READ ARRAY
AI03619
YES
READ STATUS
(ERASE RESUME)
YES c
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Figure 32. Command Interface and Program Erase Controller Flowchart (c).
B C
PROGRAM
(READ STATUS)
READ STATUS READ ARRAY
YES
READY ? NO
Program/Erase Controller Status bit in the Status Register
B0h YES NO FFh PROGRAM SUSPEND NO PROGRAM SUSPENDED YES YES
NO
READ STATUS
READY ? NO
WAIT FOR COMMAND WRITE
YES
READ STATUS
READ STATUS
YES
70h NO
READ SIGNATURE
YES
90h NO
CFI QUERY
YES
98h NO
READ ARRAY
NO
D0h
YES
READ STATUS
(PROGRAM RESUME)
AI00618
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M58LW032C
REVISION HISTORY Table 32. Document Revision History
Date 11-Mar-2002 10-Jul-2002 Version -01 -02 First Issue (Data Brief) Document expanded to full Product Preview Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 02 equals 2.0). Word Effective Programming Time modified. Program Write Buffer and Block Erase Time parameters modified in Table 9. Speed Class 90ns added. VDD, VDDQ, VSS and VSSQ signal descriptions modified. Figure 12, Asynchronous Latch Controlled Bus Read AC Waveforms, modified. REVISION HISTORY moved to after the appendices. Table 9, Program, Erase Times and Program Erase Endurance Cycles table modified. All DU connections changed to NC in Table 4, TBGA64 Connections (Top view through package). VIL max and VIH min modified in Table 14, DC Characteristics. Block Protect setup command address modified in Table 5, Commands. Data and Descriptions clarified in CFI Table 31, Extended Query information. Document promoted to full datasheet. Summary Description clarified, Bus Operations clarified, Smart Protection added, Read Modes section added, Status Register and Configuration Register bit nomenclature modified, VPEN Invalid Error clarified in Flowcharts. Lead-free packing options added to Ordering Information Scheme. Revision Details
06-Aug-2002
2.1
02-Sep-2002
2.2
16-Dec-2002
2.3
29-Apr-2003
3.0
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M58LW032C
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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